Efficiency Analysis in Reconfigurable High Performance Computing Systems

Authors

  • Martín Morales Universidad Nacional de la Patagonia San Juan Bosco - Argentina
  • Eduardo Kunysz Universidad Nacional de la Patagonia San Juan Bosco - Argentina
  • Jorge Osio Universidad Nacional de la Patagonia San Juan Bosco - Argentina
  • José Rapallini Universidad Nacional de la Patagonia San Juan Bosco - Argentina

DOI:

https://doi.org/10.33414/rtyc.33.23-28.2018

Keywords:

HPRC, FPGA, Parallel Computing

Abstract

The purpouse of this project is to introduce the architectures and characteristics for new technics of high performance computing paralleling process. As an option of optimization, performance and high energy efficient is propose a new paradigm in supercomputers design. This alternative has came with logic array technology as a part of high performance reconfigurable computer (HPRC).

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Published

2018-10-17

How to Cite

Morales, M., Kunysz, E., Osio, J., & Rapallini, J. (2018). Efficiency Analysis in Reconfigurable High Performance Computing Systems. Technology and Science Magazine, (33), 23–28. https://doi.org/10.33414/rtyc.33.23-28.2018

Issue

No. 33 (2018): CoNaIISI 2016

Section

Artículos